During operation, some microcomputers assign, or map, memory resources such as RAM, ROM, and Input/Output (I/O) registers to a unique address range from which the user may access them. Flexibility in determining the address range for each memory resource is desirable for general purpose microcomputers. This flexibility allows the user to position the most frequently used memory resources in the more quickly accessed address ranges. In some general microcontrollers, the first portion of memory is located in the "direct addressing mode" range. Instructions which use the direct addressing mode assume that the high order byte of a sixteen bit address is $00. The instructions may then be accessed with a one byte address rather than a two byte address. Therefore, the instructions use one less byte of memory space and are serviced in at least one less cycle of execution time than instructions in other addressing ranges. Maximum efficiency may then be achieved by locating the most frequently accessed memory resources in the direct addressing mode address space. The user may also modify the address range of memory resources in the microcomputer to insure compatibility with the memory resources of external systems.
In earlier microcontrollers, such as the Motorola MC68HC11A8, the user modifies the position of RAM and I/O register memory resources in a memory map by programming predetermined bits in the map register. Following the repositioning of the memory resources, however, portions of the relocated resources may be overlapped. Address decode logic within the microcomputer is provided to protect against such conflicts among memory resources. Prioritization logic disables the least important resource and allows the more important resource to be accessed without interference. For example, if an overlap between internal RAM memory address locations and the I/O register address locations occurs, the lower priority internal RAM address locations are disabled and the I/O registers are accessed without interference. The internal RAM memory addresses which overlap the addresses of the I/O registers will always be disabled so those addresses can no longer be used for the storage of information. The internal RAM is often limited in size, however, and the user may not be able to sacrifice the portion of the RAM which conflicts with a higher priority memory resource. For example, in the MC68HC11A8, if both the I/O register block and the internal RAM memory resources are positioned at the same starting address, a quarter of the internal RAM memory resource is disabled. Because such a significant portion of the internal RAM is disabled, the user might be forced to sacrifice the most efficient operation of the system to insure that adequate memory space exists. U.S. Pat. No. 4,649,476 discusses the MC68HC11A8 implementation in greater detail and is hereby incorporated herein by reference.